半导体学报2009，Vol.30Issue(5)：103-108,6.DOI:10.1088/1674-4926/30/5/055010
A 16-bit cascaded sigma-delta pipeline A/D converter
A 16-bit cascaded sigma-delta pipeline A/D converter
Li Liang 1Li Ruzhang 1Yu Zhou 1Zhang Jiabin 1Zhang Jun'an1
作者信息
- 1. National Key Laboratory of Analog ICs, The 24th Institute, China Electronics Technology Group Corporation, Chongqing 400060, China
- 折叠
摘要
Abstract
A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.关键词
multi-bit sigma-delta ADC/oversampling/pipeline/digital filter/switched capacitorKey words
multi-bit sigma-delta ADC/oversampling/pipeline/digital filter/switched capacitor分类
信息技术与安全科学引用本文复制引用
Li Liang,Li Ruzhang,Yu Zhou,Zhang Jiabin,Zhang Jun'an..A 16-bit cascaded sigma-delta pipeline A/D converter[J].半导体学报,2009,30(5):103-108,6.
