半导体学报2009，Vol.30Issue(4)：104-110,7.DOI:10.1088/1674.4926/30/4/045008 EEACC:6150D;1280
A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner
A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner
摘要
Abstract
This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage.The receiver occupies 300×500/μm2.With the novel half rate period calibration clock data recovery(CDR)circuit,the receiver consumes 52 mW power.The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE).关键词
serial link/receiver/CDR/equalizerKey words
serial link/receiver/CDR/equalizer分类
电子信息工程引用本文复制引用
Gao Zhuo,Yang Zongren,Zhao Ying,Yang Yi,Zhang Lu,Huang Lingyi,Hu Weiwu..A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner[J].半导体学报,2009,30(4):104-110,7.基金项目
Project supported by the State Key Development Program for Basic Research of China(No.2005CB321600),the National High Technology Development Research and Program of China(No.2008AA110901),the National Natural Science Foundation of China(Nos.60801045,60803029,60673146,60603049),and the Beijing Natural Science Foundation(No.4072024). （No.2005CB321600）
