北京大学学报（自然科学版）2007，Vol.43Issue(1)：109-112,4.
一种通用的可编程双模分频器
A Generic Programmable Dual Modulus Divider
摘要
Abstract
A programmable dual modulus divider is proposed. The circuit mainly includes three building blocks: prescaler, 8-bit programmable counter and ∑△ modulator. Two operation modes (integer/fractional-N) are achieved by switching on/off the output signal of the ∑△ modulator. Only a programmable counter is needed for the swallow pulse divider. The prescaler was designed by using the improved dynamic TSPC triggers, and the other blocks were realized by the way of digital synthesis, placing and routing.Based on 0. 18 μm 1.8 V CMOS technology, SpectreVerilog simulations verify that it can operate within the division ratio of 56-2 047 with 2 GHz maximum operation frequency and ＜ 4 mA current dissipation. The circuit is very simple and can be used in the high performance PLL frequency synthesizer.关键词
分频器/∑△调制器/计数器/三线接口Key words
divider/∑△ modulator/counter/3-wire bus分类
信息技术与安全科学引用本文复制引用
黄水龙,王志华..一种通用的可编程双模分频器[J].北京大学学报（自然科学版）,2007,43(1):109-112,4.基金项目
国家高技术研究发展计划(60475018)和国家重点基础研究发展规划(G2000036508)资助项目 （60475018）
