半导体学报2000，Vol.21Issue(12)：1157-1163,7.
A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's
A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's
李力南 1钱鹤1
作者信息
- 1. Microeletronics R ＆ D Center, The Chinese Academy of Sciences, Beijing 100029,China
- 折叠
摘要
Abstract
Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on-chip integrated inductor, a concise method to increase the Q factor has been ob tained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5 % compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.关键词
CMOS RF IC/integrated on-chip inductor/Q factorKey words
CMOS RF IC/integrated on-chip inductor/Q factor分类
信息技术与安全科学引用本文复制引用
李力南,钱鹤..A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's [J].半导体学报,2000,21(12):1157-1163,7.
