医学信息2004，Vol.17Issue(3)：118-122,5.
DFT Techniques in DSP Chip Core NDSP25
DFT Techniques in DSP Chip Core NDSP25
XUE Jing 1BAI Yong-qiang 1DENG Zheng-hong 1ZHENG Wei1
作者信息
- 1. Computer School of Northwestern Polytechnical University,Xi'an 710072,China
- 折叠
摘要
Abstract
Design for Testability(DFT) is critical in chip design.DFT techniques insert hardware logic to an original design,in order to improve testability of the chip,and thus reduce test cost significantly.In this paper,we introduces the most frequently used DFT techniques,then put emphasis on the DFT policy and the DFT realization of the NDSP25 chip core,and analyses the result at last.关键词
NDSP25 Chip Core/design for testability(DFT)/built-in self-testKey words
NDSP25 Chip Core/design for testability(DFT)/built-in self-test分类
医药卫生引用本文复制引用
XUE Jing,BAI Yong-qiang,DENG Zheng-hong,ZHENG Wei..DFT Techniques in DSP Chip Core NDSP25[J].医学信息,2004,17(3):118-122,5.
