半导体学报2004，Vol.25Issue(10)：1221-1226,6.
应用400℃低温Si技术制备应变Si沟道pMOSFET
Strained Si Channel Heterojunction pMOSFET Using 400℃ LT-Si Technology
摘要
Abstract
A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At the same time,the threading dislocations (TDs) are hold back from propagating to the surface.As a result,the thickness of relaxed Si1-xGex epitaxy layer on bulk silicon is reduced from several micrometers using UHVCVD to less than 400nm(x=0.2),which will improve the heat dissipation of devices.AFM tests of strained Si surface show RMS is less than 1.02nm.The DC characters measured by HP 4155B indicate that hole mobility μp has 25% of maximum enhancement compared to that of bulk Si pMOSFET processed similarly.关键词
锗硅/低温硅/弛豫/线位错Key words
SiGe/low-temperature Si/strain relaxation/threading dislocation分类
信息技术与安全科学引用本文复制引用
梅丁蕾,杨谟华,李竞春,于奇,张静,徐婉静,谭开洲..应用400℃低温Si技术制备应变Si沟道pMOSFET[J].半导体学报,2004,25(10):1221-1226,6.基金项目
模拟集成电路国家重点实验室基金资助项目(合同号:2000JS09.3.1.DZ02) （合同号:2000JS09.3.1.DZ02）
