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An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

Gao Peijun Oh N J Min Hao

半导体学报2009，Vol.30Issue(8)：123-126,4.
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半导体学报2009，Vol.30Issue(8)：123-126,4.DOI:10.1088/1674-4926/30/8/085004

An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

Gao Peijun 1Oh N J 2Min Hao1

作者信息

  • 1. State Key Laboratory of ASIC & System,Fudan University,Shanghai 201203,China
  • 2. Department of Electronic Engineering,Chungju National University,Korea
  • 折叠

摘要

Abstract

om 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

关键词

close-in phase noise/vertical-NPN/flicker noise/VCO

Key words

close-in phase noise/vertical-NPN/flicker noise/VCO

分类

信息技术与安全科学

引用本文复制引用

Gao Peijun,Oh N J,Min Hao..An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process[J].半导体学报,2009,30(8):123-126,4.

基金项目

Project supported by the Innovation Founding of Fudan University, China. （）

半导体学报

OA北大核心CSCDCSTPCDEI

1674-4926

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