半导体学报2008，Vol.29Issue(7)：1298-1304,7.
一种用于短距离器件的带自校准的∑-Δ分数分频频率综合器
AΣ-ΔFractional-N PLL Frequency Synthesizer with AFC for SRD Applications
章华江 1胡康敏 1洪志良1
作者信息
- 1. 复旦大学专用集成电路与系统国家重点实验室,上海,201203
- 折叠
摘要
Abstract
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0. 35μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly, an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than -60dBc. The chip area is 1.5mm×1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.关键词
短距离器件/锁相环/自适应频率校准/频率综合器/sigma-deltaKey words
short range device/phase locked loop/adaptive frequency calibration/frequency synthesizer/sigma-delta分类
信息技术与安全科学引用本文复制引用
章华江,胡康敏,洪志良..一种用于短距离器件的带自校准的∑-Δ分数分频频率综合器[J].半导体学报,2008,29(7):1298-1304,7.
