半导体学报2001，Vol.11Issue(2)：134-137,4.
High Performance 70nm CMOS Devices
High Performance 70nm CMOS Devices
摘要
Abstract
A high performance 70nm CMOS device has been demonstrated for thefirst time in the continent， China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly-Si gate electrode, novel super-steep retrograde channel doping by heavy ion implantation, ultra-shallow S/D extension formed by Ge PAI(Pre-Amorphism Implantation) plus LEI（Low Energy Implantation）, thin and low resistance Ti-SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages，Gm and off current are 0.28V，490mS．mm－1 and 0.08nA/μm for NMOS and -0.3V，340mS*mm－1 and 0.2nA/μm for PMOS, respectively. Delays of 23.5ps/stage at 1.5V, 17.5ps/stage at 2.0V and 12.5ps/stage at 3V are achieved in the 57-stage unloaded 100nm CMOS ring oscillator circuits.关键词
高性能/70nm CMOS器件/源漏延伸区/氮化栅氧化介质/锗预无定形注入/自对准硅化物分类
信息技术与安全科学引用本文复制引用
徐秋霞,钱鹤,殷华湘,贾林,季红浩,陈宝钦,朱亚江,刘明..High Performance 70nm CMOS Devices[J].半导体学报,2001,11(2):134-137,4.基金项目
国家攀登计划资助项目． （）
