东南大学学报（英文版）2005，Vol.21Issue(2)：141-144,4.
10 Gbit/s 0.25 μm CMOS 1:4分接器
10 Gbit/s 0.25 μm CMOS 1:4 demultiplexer
摘要
Abstract
A 10 Gbit/s (STM-64,OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock was achieved in TSMC s standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique.All of the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed and suppress common mode distortions.This DEMUX is featured by constant-delay buffers to generate a 4-phase clock and adjust skews of the four channel outputs.The fabricated DEMUX operates error free at 10 Gbit/s by 231-1 pseudorandom bit sequences (PRBS) via on-wafer testing.The measured root mean square (rms) jitter,rising and failing edge of the eye-diagram are 11,123 and 137 ps,respectively.The chip size is 0.9 mm×1.2 mm and the power dissipation is 550 mW with a 3.3 V supply.关键词
光接收机/CMOS/分接器/锁存器Key words
optical receive/complementary metal-oxide-semiconductor (CMOS)/demultiplexer (DEMUX)/latch分类
信息技术与安全科学引用本文复制引用
丁敬峰,王志功,朱恩,王贵,夏春晓,熊明珍..10 Gbit/s 0.25 μm CMOS 1:4分接器[J].东南大学学报（英文版）,2005,21(2):141-144,4.基金项目
The National High Technology Research and Development Program of China (863 Program) (No.2002AA312230,2003AA31G030). （863 Program）
