半导体学报2005，Vol.26Issue(8)：1524-1531,8.
CMOS集成频率综合器的稳定性补偿
A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation
摘要
Abstract
A complete closed-loop third-order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process, voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.关键词
频率综合器/闭环三阶s域/环路参数/PVT变化/稳定性/变化裕量Key words
frequency synthesizer/closed-loop third-order s-domain/loop parameters/PVT variation/stability/variation margin分类
信息技术与安全科学引用本文复制引用
何捷,唐长文,闵昊,洪志良..CMOS集成频率综合器的稳定性补偿[J].半导体学报,2005,26(8):1524-1531,8.基金项目
上海市科学技术委员会2003年度集成电路设计科技专项(批准号:037062019)和上海应用材料研究与发展基金(批准号:0425)资助项目Project supported by the Shanghai Science & Technology Committee,China Under System-Design-Chip(SDC) Program(No. 037062019) and the Shanghai AM(Applied Material) Funds(No. 0425) （批准号:037062019）
