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An asynchronous pipeline architecture for the low-power AES S-box

Zeng Yonghong Zou Xuecheng Liu Zhenglin

高技术通讯(英文版)2008,Vol.14Issue(2):154-159,6.
高技术通讯(英文版)2008,Vol.14Issue(2):154-159,6.

An asynchronous pipeline architecture for the low-power AES S-box

An asynchronous pipeline architecture for the low-power AES S-box

Zeng Yonghong 1Zou Xuecheng 2Liu Zhenglin1

作者信息

  • 1. Research Center for VLSI and Systems, Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, P.R.China
  • 2. College of Electronic Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, P.R.China
  • 折叠

摘要

Abstract

To obtain a low-power and compact implementation of the advanced encryption standard (AES) S-box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. (1) Level-sensitive latches were inserted in data path to block the propagation of the dynamic hazards, which lowered the power of data path circuit. (2) Operations of latches were controlled by latch controllers based on presented asynchronous sequence element: LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. (3) Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor (CMOS) process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty (11.7%) compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelligent property (IP) embedded in the targeted systems such as wireless sensor networks (WSN), smartcards and radio frequency identification (RFID).

关键词

advanced encryption standard (AES)/S-box/asynchronous pipeline/composite field

Key words

advanced encryption standard (AES)/S-box/asynchronous pipeline/composite field

分类

建筑与水利

引用本文复制引用

Zeng Yonghong,Zou Xuecheng,Liu Zhenglin..An asynchronous pipeline architecture for the low-power AES S-box[J].高技术通讯(英文版),2008,14(2):154-159,6.

基金项目

Supported by the National High Technology Research and Development Programme of China (Grant No. 2006AA01Z226) and by the Project (Grant No. 2006Z001B) Supported by the Scientific Research Foundation of Huazhong University of Science and Technology. (Grant No. 2006AA01Z226)

高技术通讯(英文版)

1006-6748

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