东南大学学报（英文版）2008，Vol.24Issue(2)：159-162,4.
应用于DVB-T的0.1 8μm CMOS可编程分频器设计
0. 18 μm CMOS programmable frequency divider design for DVB-T
摘要
Abstract
The implementation of a programmable frequencydivider, which is one of the components of the phase-locked loop(PLL) frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) and other modem communication systems, ispresented. By cooperating with a dual-modulus prescaler, thisdivider can realize an integer frequency division from 926 to1 387. Besides the traditional standard cell design flow, such aslogic synthesis, placement and routing, the interactions betweenfront-end and back-end are also considered to optimize the designflow under deep submicron technology. By back-annotating theback-end information to front-end design, a custom wire-loadmodel is created which is more practical compared with thedefault model. This divider has been fabricated in TSMC 0.18um CMOS technology using Artisan standard cell library. Thechip area is 675um×475um and the power consumption isabout 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency divisionwith high precision.关键词
可编程分频器/频率综合器/标准单元/数字电视地面广播Key words
programmable frequency divider/ frequencysynthesizer/ standard cell/ DVB-T分类
信息技术与安全科学引用本文复制引用
胡庆生,仲建锋,何小虎..应用于DVB-T的0.1 8μm CMOS可编程分频器设计[J].东南大学学报（英文版）,2008,24(2):159-162,4.基金项目
The National Natural Science Foundation of China(No.60472057). （No.60472057）
