半导体学报2008，Vol.29Issue(9)：1740-1744,5.
高性能微处理器中一种改进的高扇入多米诺电路设计与实现
An Improved High Fan-in Domino Circuit for High Performance Microprocessors
摘要
Abstract
An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0. 13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is 115μm2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.关键词
高扇入/多米诺逻辑/高性能/保持管Key words
high fan-in/domino logic/high performance/keeper transistor分类
信息技术与安全科学引用本文复制引用
冯超超,陈迅,衣晓飞,张民选..高性能微处理器中一种改进的高扇入多米诺电路设计与实现[J].半导体学报,2008,29(9):1740-1744,5.基金项目
国家高技术研究发展计划资助项目(批准号:2005AA110020) Project supported by the National High-Tech Research and Development Program of China (No. 2005AA110020) （批准号:2005AA110020）
