半导体学报2005，Vol.26Issue(11)：2062-2068,7.
一种基于编码的低硬件开销的测试数据压缩方法
An Efficient Test Data Compression Technique Based on Codes
摘要
Abstract
This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters:compression ratio, test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.关键词
测试数据压缩/不确定位填充/SoC测试/混合游程编码Key words
test data compression/unspecified bits assignment/system-on-a-chip test/hybrid run-length codes分类
信息技术与安全科学引用本文复制引用
方建平,郝跃,刘红侠,李康..一种基于编码的低硬件开销的测试数据压缩方法[J].半导体学报,2005,26(11):2062-2068,7.基金项目
国家高技术研究发展计划(批准号:2003AA1Z1630)和国家自然科学基金(批准号:60206006)资助项目Project supported by the National High Technology Research and Development Program of China(No. 2003AA1Z1630) and the National Natural Science Foundation of China(No. 60206006) （批准号:2003AA1Z1630）
