半导体学报2006，Vol.27Issue(12)：2106-2111,6.
应用于2Mb/s GMSK调制的CMOS低功耗全差分Sigma-Delta频率综合器
A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation
摘要
Abstract
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying(GMSK)modulation is presented.A pre-compensation fractional-N phase-locked loop(PLL)is adopted in the modulator.The transfer function of the type-Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out.Methods to calibrate the important loop parameters are introduced.A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design.The designed circuits are simulated in a 0.18μm 1P6M CMOS process.The power consumption of the PLL is only about 11mW with the low power consideration in building blocks design,and the data rate of the modulator can reach 2Mb/s.关键词
互补-MOS型集成电路/分数-N/高斯滤波最小频移键控/锁相环/∑-△Key words
CMOS/fractional-N/Gaussian minimum shift keying/phase-locked loop/sigma-delta分类
信息技术与安全科学引用本文复制引用
张利,池保勇,姚金科,王志华,陈弘毅..应用于2Mb/s GMSK调制的CMOS低功耗全差分Sigma-Delta频率综合器[J].半导体学报,2006,27(12):2106-2111,6.基金项目
Project supported by the State Key Development Program Basic Research of China(No.G2000036508)and the National Natural Science Foundation of China (Nos.90407006,60475018)国家重点基础研究发展计划(批准号:G2000036508)和国家自然科学基金(批准号:90407006,60475018) 资助项目 （No.G2000036508）
