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Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform

高技术通讯（英文版）2007，Vol.13Issue(3)：297-301,5.
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高技术通讯（英文版）2007，Vol.13Issue(3)：297-301,5.

Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform

Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform

1

作者信息

  • 1. Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China;Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China;Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China;Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China;Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China
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摘要

Abstract

A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television (HDTV) system-on-a-chip (SoC) platform,especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property (IP), the interrupt controller has reusability and expandability with the layered structure.

关键词

HDTV SoC, interrupt controller, MIPS processor core

Key words

HDTV SoC, interrupt controller, MIPS processor core

分类

信息技术与安全科学

引用本文复制引用

..Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform[J].高技术通讯（英文版）,2007,13(3):297-301,5.

基金项目

Supported by the High Technology Research and Development Programme of China (2003AA1Z1070) （2003AA1Z1070）

高技术通讯（英文版）

OAEI

1006-6748

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