电子器件2006，Vol.29Issue(2)：314-317,4.
1.2 GHz CMOS全集成锁相环的设计
Design of a Fully Integrated 1.2 GHz CMOS Phase-Locked Loop
赵坤 1满家汉 1叶青 1叶甜春1
作者信息
- 1. 中国科学院微电子研究所,北京,100029
- 折叠
摘要
Abstract
On the base of analyzing the factors affecting the performance of the PLL, the corresponding scheme for optimization is presented and a 1.2 GHz LC phase-locked loop (PLL) is designed. The circuit design of the PLL that consists of a LC-tank circuit, prescaler, frequency divider, phase/frequency detector, charge pump that includes a bandgap current reference and a passive loop filter is introduced and the simulation results are given. The PLL is designed in SMIC 0.18 μm 3.3 V 1P6M CMOS RF technology and the passive loop filter is also on-chip and no off-chip components are needed.关键词
锁相环/压控振荡器/预分频器/电荷泵/带隙基准电流源Key words
phase-locked loop/VCO/prescaler/charge pump/bandgap current reference分类
信息技术与安全科学引用本文复制引用
赵坤,满家汉,叶青,叶甜春..1.2 GHz CMOS全集成锁相环的设计[J].电子器件,2006,29(2):314-317,4.
