电子器件2009，Vol.32Issue(2)：347-350,4.
一种复杂SoC可测性的设计与实现
Design and Implementation of DFF for a Complex SoC
摘要
Abstract
With the increasing complexity and chip scale of SoC,DFT(Design-for-test) has become a more impor-tant and difficult process.A system-level DFT strategy for a SoC based on 32-bit RISC CPU is presented.Accord-ing tO the characteristic of different parts of SoC,test solutions for digital logic,SRAM,RISC CPU and digital PLL in the SoC are discussed.The test methods include internal scan design,SRAM BIST,BSD and function test.The results show the higher fault coverage and smaller area overhead ale gotten关键词
可测性设计/扫描链/自动测试向量生成/存储器内建自测试/SoCKey words
DFT/scan chain/ATPG/MBIST/SoC分类
信息技术与安全科学引用本文复制引用
虞致国,魏敬和,杨兵..一种复杂SoC可测性的设计与实现[J].电子器件,2009,32(2):347-350,4.基金项目
江苏省博士后科研计划项目资助 （）
