一种快捕获宽调节范围的锁相环OA北大核心CSCDCSTPCD
A Fast Acquisition PLL with Wide Tuning Range
提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获…查看全部>>
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties. Measured results show that the experimental chip, implemented in a standard 0.5μm 5V CMOS logic process, has an acquisition time of about 150ns at 37% f…查看全部>>
葛岩;贾嵩;叶红飞;吉利久
北京大学微电子学研究所,北京,100871北京大学微电子学研究所,北京,100871北京大学微电子学研究所,北京,100871北京大学微电子学研究所,北京,100871
电子信息工程
锁相环快捕获低抖动宽调节范围
PLLfast acquisitionlow jitterwide tuning range
《半导体学报》 2007 (3)
365-371,7
Project supported by the National Advanced Research Program of China 国家预先研究资助项目
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