半导体学报2006，Vol.27Issue(3)：448-453,6.
高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件
A High Performance Sub-100nm Nitride/Oxynitride Stack Gate Dielectric CMOS Device with Refractory W/TiN Metal Gates
钟兴华 1周华杰 1林钢 1徐秋霞1
作者信息
- 1. 中国科学院微电子研究所,北京,100029
- 折叠
摘要
Abstract
By complementing the equivalent oxide thickness (EOT) of a 1.7nm nitride/oxynitride (N/O) stack gate dielectric (EOT = 1.7nm) with a W/TiN metal gate electrode, metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS = ± 1.5Vand VGS = ± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of107.4mV/dec,DIBL of 54.46mV/V, and Vth of - 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect,effectively reduced gate tunneling leakage,and improved device reliability.关键词
等效氧化层厚度/氮氧叠层栅介质/W/TiN金属栅/非CMP平坦化Key words
equivalent oxide thickness/nitride/oxynitride gate dielectric stack/W/TiN metal gate/non-CMP planarization分类
信息技术与安全科学引用本文复制引用
钟兴华,周华杰,林钢,徐秋霞..高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件[J].半导体学报,2006,27(3):448-453,6.
