电子器件2008，Vol.31Issue(2)：461-464,4.
单芯片高效率降压DC-DC芯片设计
Design of a Monolithic High-Efficiency Step-Down DC-DC Converter
闫峰 1孙伟锋 1夏晓娟 1陆生礼1
作者信息
- 1. 东南大学国家专用集成电路工程技术研究中心,南京,210096
- 折叠
摘要
Abstract
This paper presents an integrated circuit design and implementation of a monolithic DC-IX；con-verter to achieve high efficiency over wide loading conditions.The converter is designed and simulated u-sing a 0.6 m twin well mixed-signal CMOS process for a supply voltage range of 2～5 V,which is tom-patible with portable battery-operated devices.The method to improve the efficiency is discussed.Simula-tion results show that the converter generates an output voltage of 1.8 V while delivering up to 500mA load current with a maximum ripple of 5 mV.The converter exhibits a maximum efficiency of 93.8%and an overall efficiency above 86.2% with the load current from 5 mA to 500 mA.关键词
电源管理/DC-DC转换器/高效率/PWM/PFMKey words
Power Management/DC-DC Converter/high efficiency/PWM／PFM分类
信息技术与安全科学引用本文复制引用
闫峰,孙伟锋,夏晓娟,陆生礼..单芯片高效率降压DC-DC芯片设计[J].电子器件,2008,31(2):461-464,4.
