东南大学学报（英文版）2006，Vol.22Issue(4)：475-478,4.
一种具有饱和处理功能的24位并行乘加单元优化设计
Optimization design of 24 bit parallel MAC unit with saturation
摘要
Abstract
An efficient design method for a 24×24 bit + 48 bit parallel saturating multiply-accumulate (MAC)unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm×132.5 μm area size has been achieved in 0.18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area (about 23.52% reduction) and less delay than those of the common saturating MAC based on standard cell library.关键词
乘加器/Booth编码/Wallace树/饱和检测/布局Key words
multiply-accumulate/Booth encoding/Wallace tree/saturation detection/layout design分类
信息技术与安全科学引用本文复制引用
张萌,贾俊波..一种具有饱和处理功能的24位并行乘加单元优化设计[J].东南大学学报（英文版）,2006,22(4):475-478,4.基金项目
The National Natural Science Foundation of China (No. 90407009), the National High Technology Research and Development Program of China(863 Program) (No. 2003AA1Z1340). （No. 90407009）
