半导体学报2007，Vol.28Issue(4)：537-541,5.
2.5Gb/s 0.18μm CMOS时钟数据恢复电路
2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit
刘永旺 1王志功 1李伟1
作者信息
- 1. 东南大学射频与光电集成电路研究所,南京,210096
- 折叠
摘要
Abstract
A 2.5Gb/s clock and data recovery (CDR) circuit is designed and realized in TSMC's standard 0.18μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization, a dynamic phase and frequency detector (PFD) is used in the PLL. The rms jitter of the recovered 2. 5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.关键词
时钟恢复/数据恢复/锁相环/动态鉴频鉴相器Key words
clock recovery/data recovery/phase locked loop/dynamic phase and frequency detector分类
电子信息工程引用本文复制引用
刘永旺,王志功,李伟..2.5Gb/s 0.18μm CMOS时钟数据恢复电路[J].半导体学报,2007,28(4):537-541,5.
