北京大学学报（自然科学版）2008，Vol.44Issue(1)：55-61,7.
一种降低流水化指令缓冲存储器泄漏功耗的设计方法
A Low-Leakage Pipelined Instruction Cache Design
摘要
Abstract
Pipelined level one instruction cache (PIL1) has been proposed to improve instru ction fetch bandwidth in high frequency processor. However, few researches in the literature have focused on reducing the leakage power in PIL1. Here,the authors observe that the PIL1 structure naturally lends itself to provide inherent lea kage power saving opportunities. Based on this observation, the authors propose to manage cache line activities according to the demand of the fetch address, which activates only the requested line and keeps others in low-voltage mode, thereby saving leakage power effectively. Simulation results demonstrate that the PIL1 leakage power is reduced by an average of 77.3%. Meanwhile,the performance degradation is only 0.32% and no timing overhead is induced.关键词
泄漏功耗/流水化指令缓冲存储器/动态电压调节Key words
leakage power/ pipelined instruction cache/ dynamic voltage scaling分类
信息技术与安全科学引用本文复制引用
孙含欣,王箫音,佟冬,程旭..一种降低流水化指令缓冲存储器泄漏功耗的设计方法[J].北京大学学报（自然科学版）,2008,44(1):55-61,7.基金项目
国家"863"计划(2004AA1Z1010)资助项目 （2004AA1Z1010）
