高技术通讯（英文版）2002，Vol.8Issue(3)：57-61,5.
A Low Power/Area Digital FIR Filter Design Based on PRF Framework
A Low Power/Area Digital FIR Filter Design Based on PRF Framework
摘要
Abstract
A novel DSP to ASIC (Application Specific Integrated Circuit) architecture desig n methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm sep arately. The authors propose a new method called PRF (ParallelingReducing-Fol-ding) framework to combine hardware optimization with algorithm simplification. In the first step,paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing,decoupling theory is used to reduce computational complexity.In the last step, folding, timemultiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework.To optimize a 3N taps FIR (Fincte Impact Response)and obtain a content result,PRF methodology framework is applied.关键词
ASIC architecture/systolic array/paralleling/reducing folding/power/area optimizationKey words
ASIC architecture/systolic array/paralleling/reducing folding/power/area optimization分类
信息技术与安全科学引用本文复制引用
..A Low Power/Area Digital FIR Filter Design Based on PRF Framework[J].高技术通讯（英文版）,2002,8(3):57-61,5.基金项目
Sponsored by HDTV Project of State Development Planning Commission P.R.China. （）
