北京大学学报（自然科学版）2007，Vol.43Issue(5)：649-653,5.
一种高效并行处理结构的H.264去块滤波器
An Effective Parallel Processing Architecture for Deblocking Filter in H.264
赵悦汐 1蒋安平1
作者信息
- 1. 北京大学信息技术学院微电子系,北京,100871
- 折叠
摘要
Abstract
An efficient parallel processing method for deblocking filter design in H.264 video coding standard is presented. In order to reduce the memory reference and make the intermediate data reused as soon as possible, an advanced filtering order is taken, and so read/write operation on external memory is executed in parallel with filtering computation. Furthermore, preloading operation is used to reduce complexity of memory structure. As a result, the processing cycles of the proposed architecture with single-port memory architecture is reduced by 9.6%-74.4% compared with the advanced architecture of previous proposals.关键词
H.264/去块效应滤波/VLSI/并行处理Key words
H.264/ deblocking filter/ VLSI/ parallel processing分类
信息技术与安全科学引用本文复制引用
赵悦汐,蒋安平..一种高效并行处理结构的H.264去块滤波器[J].北京大学学报（自然科学版）,2007,43(5):649-653,5.
