半导体学报2007，Vol.28Issue(5)：692-695,4.
2.5Gb/s/ch 0.18μm CMOS数据恢复电路
2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit
刘永旺 1王志功 1李伟1
作者信息
- 1. 东南大学射频与光电集成电路研究所,南京,210096
- 折叠
摘要
Abstract
A 2.5Gb/s/ch data recovery(DR)circuit is designed for an SFI-5 interface.To make the parallel data bit-synchronization and reduce the bit error rate(BER),a delay locked loop(DLL)is used to place the center of the data eye exactly at the rising edge of the data-sampling clock.A single channel DR circuit was fabricated in TSMC's standard 0.18μm CMOS process.The chip area is 0.46mm2.With a 231-1 pseudorandom bit sequence(PRBS)input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps.The sensitivity of the single channel DR is less than 20mV with 10-12 BER.关键词
数据恢复/延迟锁相环/位同步Key words
data recovery/delay locked loop/bit-synchronization分类
电子信息工程引用本文复制引用
刘永旺,王志功,李伟..2.5Gb/s/ch 0.18μm CMOS数据恢复电路[J].半导体学报,2007,28(5):692-695,4.
