半导体学报2009，Vol.30Issue(2)：69-73,5.DOI:10.1088/1674-4926/30/2/025006
A 13-bit, 8 MSample/s pipeline A/D converter
A 13-bit, 8 MSample/s pipeline A/D converter
郭丹丹 1李福乐 1张春 1王志华1
作者信息
- 1. Institute of Microelectronics, Tsinghua University, Beijing 100084, China
- 折叠
摘要
Abstract
A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm IP6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.关键词
analog-to-digital converter/ pipeline/ high-accuracy/ sampling circuit/ power programmableKey words
analog-to-digital converter/ pipeline/ high-accuracy/ sampling circuit/ power programmable分类
信息技术与安全科学引用本文复制引用
郭丹丹,李福乐,张春,王志华..A 13-bit, 8 MSample/s pipeline A/D converter[J].半导体学报,2009,30(2):69-73,5.
