半导体学报2006，Vol.27Issue(5)：783-786,4.
用于降低CMOS集成电路中晶体管跨导标准差的偏置电流补偿电路
Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits
摘要
Abstract
A simple and successful method for the stability enhancement of integrated circuits is presented.When the process parameters,temperature,and supply voltage are changed,according to the simulation results,this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case.This method can be used in CMOS LC oscillator design.关键词
CMOS/跨导/集成电路/晶体管Key words
CMOS/transconductance/integrated circuits/transistor分类
信息技术与安全科学引用本文复制引用
冒小建,杨华中,汪蕙..用于降低CMOS集成电路中晶体管跨导标准差的偏置电流补偿电路[J].半导体学报,2006,27(5):783-786,4.基金项目
国家自然科学基金资助项目(批准号:90407011,60025101,90207001,90307016)Project supported by the National Natural Science Foundation of China(Nos.90407011,60025101,90207001,and 90307016) （批准号:90407011,60025101,90207001,90307016）
