半导体学报2006，Vol.27Issue(5)：804-811,8.
亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计
Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies
郭宝增 1宫娜 1汪金辉2
作者信息
- 1. 河北大学电子信息工程学院,保定,071002
- 2. 北京工业大学电子信息与控制工程学院,北京,100022
- 折叠
摘要
Abstract
Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE.The simulation results show that the proposed circuits effectively lower the active power,reduce the total leakage current,and enhance speed under similar noise immunity conditions.The active power of the two proposed circuits can be reduced by up to 8.8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage.At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4%,respectively.Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.关键词
低功耗/漏电流/多米诺或门/噪声容限Key words
low power/leakage current/OR dominos/noise immunity分类
信息技术与安全科学引用本文复制引用
郭宝增,宫娜,汪金辉..亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计[J].半导体学报,2006,27(5):804-811,8.
