重庆大学学报(自然科学版)2001，Vol.24Issue(3)：80-82,3.
FFT处理器的高密度可编逻辑器件实现
Complex Programmable Logic Devices Implementation of FFT Processor
摘要
Abstract
In order to accelerate the working speed of a FFT processor, this paper presents a hardware structure of a FFT processor, which is suitable for CPLD , and the 128-point FFT single-chip processor is realized by means of FLEX10K CPLD and MAX+PLUS II software. The calculation time of the processor is less than 230uS. The research proves that the combination of CPLD and FFT increases the working speed of FFT processors and raise the level of application .关键词
快速傅立叶变换/可编逻辑器件/逻辑设计分类
信息技术与安全科学引用本文复制引用
唐治德,姚玉坤,刘晓明..FFT处理器的高密度可编逻辑器件实现[J].重庆大学学报(自然科学版),2001,24(3):80-82,3.
