半导体学报2008，Vol.29Issue(5)：883-888,6.
90nm CMOS工艺SRAM的优化及应用
Optimization and Application of SRAM in 90nm CMOS Technology
摘要
Abstract
This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield ofSRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order toreduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM isconstructed. The optimized LPSR SRAM64K×32 is used in SoC and the testing method of the LPSR SRAM64K×32 is al-so discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies5.6mm×5.6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K×32 ob-tains 17.301% power savings and the yield of the LPSR SRAM64K×32s per wafer is improved by 13. 255%.关键词
优化/低功耗自我修复SRAM/冗余逻辑/电源开启/关闭状态Key words
optimization/ LPSR SRAM/ redundancy logic/ power on/off states分类
信息技术与安全科学引用本文复制引用
周清军,刘红侠..90nm CMOS工艺SRAM的优化及应用[J].半导体学报,2008,29(5):883-888,6.基金项目
Project supported by the National Natural Science Foundation of China No. 60206006), the National Defense Pre-Research Foundation of China(No. 51308040103) and the Xi'an Applied Materials Innovation Fund (No. XA-AM-200701) （No. 51308040103）
国家自然科学基金(批准号:60206006)，国防预研基金(批准号:51308040103)以及西安应用材料创新基金(批准号:XA-AM-200701)资助项目 （批准号:60206006）
