半导体学报2008，Vol.29Issue(1)：88-92,5.
一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环
Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector
摘要
Abstract
A fast-locking, low-jitter, phase-locked loop (PLL) with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time.The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45°. The PLL is fabricated in 0.18μm CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6mW at a 1.8V supply.关键词
锁相环/鉴频鉴相器/电压控制振荡器/抖动/锁定时间Key words
phase locked loop/ phase-frequency detector/ voltage-controlled oscillator/ jitter/ locking time分类
电子信息工程引用本文复制引用
陈莹梅,王志功,章丽..一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环[J].半导体学报,2008,29(1):88-92,5.基金项目
国家高技术研究发展计划资助项目(批准号:2006AA01Z239) （批准号:2006AA01Z239）
