半导体学报2009，Vol.30Issue(6)：88-93,6.DOI:10.1088/1674-4926/30/6/065002
Current mode ADC design in a 0.5-μm CMOS process
Current mode ADC design in a 0.5-μm CMOS process
Sun Yong 1Lai Fengchang 1Ye Yizheng1
作者信息
- 1. Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China
- 折叠
摘要
Abstract
This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.关键词
current mode/analog to digital converter/pipelinedKey words
current mode/analog to digital converter/pipelined分类
信息技术与安全科学引用本文复制引用
Sun Yong,Lai Fengchang,Ye Yizheng..Current mode ADC design in a 0.5-μm CMOS process[J].半导体学报,2009,30(6):88-93,6.
