电子器件2008，Vol.31Issue(3)：915-918,4.
一种应用于8B/10B编码串并转换电路的低功耗LVDS接收器设计
Low-Power LVDS Receiver with Equalization for 8B/10B SerDes
摘要
Abstract
LVDS (Low-Voltage Differential Signals) is one of the mainstream techniques for SerDes (seriali- zer/deserializer) I/Os. This paper presents the design and implementation of a LVDS receiver for 8B/10B SerDes. The receiver is fully compatible with IEEE Std 1596. 3-1996 standard, and supports input com-mon-mode range of 0.05 V to 2.35 V and minimum input differential signal of 100 mV. It can operate at up to 1.6 Gb/s over at least 40-inch FR4 stripline with equalization and has only 3 mW power consump-tion. The design is based on 0.18μm 1.8 V/3.3 V CMOS technology using both thick (3.3 V) and thin(1.8 V) gate oxide devices.关键词
低电压差分信号/接收电路/串并转换电路/低功耗/8B/10B编码Key words
low-voltage differential signaling(LVDS) / Receiver/ SerDes/ low power/ 8B/10B分类
信息技术与安全科学引用本文复制引用
尤扬,陈岚..一种应用于8B/10B编码串并转换电路的低功耗LVDS接收器设计[J].电子器件,2008,31(3):915-918,4.基金项目
国家高科技研究和发展项目(National High Technique Research.h and Develolmaent Programof China)(2006AA01A102) （National High Technique Research.h and Develolmaent Programof China）
