半导体学报2009，Vol.30Issue(5)：91-95,5.DOI:10.1088/1674-4926/30/5/055007
A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS
A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS
摘要
Abstract
A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875 × 640 μm2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.关键词
demultiplexer/latch/CML/design philosophyKey words
demultiplexer/latch/CML/design philosophy分类
信息技术与安全科学引用本文复制引用
Zhang Changchun,Wang Zhigong,Shi Si,Li Wei..A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS[J].半导体学报,2009,30(5):91-95,5.基金项目
Project supported by the National High Technology Research and Development Program of China (No.2007AA01Z2a5). （No.2007AA01Z2a5）
