半导体学报2008，Vol.29Issue(5)：930-935,6.
时钟数据恢复电路中相位插值器的分析和设计
Analysis and Design of a Phase Interpolator for Clock and Data Recovery
孙烨辉 1江立新2
作者信息
- 1. 南开大学信息技术科学学院,天津,300071
- 2. IDT科技(上海)有限公司,上海,200233
- 折叠
摘要
Abstract
In this paper, a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model issetup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output ampli-tude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new enco-ding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results showthat the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpola-tor. To alleviate this undesired effect,two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOSphase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phaseinterpolator is 1roW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone outputphase and good linearity.关键词
相位插值器/时钟数据恢复/CMOSKey words
phase interpolator/ clock and data recovery/ CMOS分类
信息技术与安全科学引用本文复制引用
孙烨辉,江立新..时钟数据恢复电路中相位插值器的分析和设计[J].半导体学报,2008,29(5):930-935,6.
