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A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

Tang Lu Wang Zhigong Xue Hong He Xiaohu Xu Yong Sun Ling

半导体学报2010，Vol.31Issue(5)：106-113,8.

半导体学报2010，Vol.31Issue(5)：106-113,8.DOI:10.1088/1674-4926/31/5/055008

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

Tang Lu ¹Wang Zhigong ¹Xue Hong ¹He Xiaohu ¹Xu Yong ¹Sun Ling²

作者信息

1. Institute of RF- & OE-ICs,Southeast University,Nanjing 210096,China
2. Institute of Sciences,PLA University of Science and Technology,Nanjing 211101,China
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摘要

关键词

PLL/down-scaling circuits/prescalers/charge pump/jitter

Key words

PLL/down-scaling circuits/prescalers/charge pump/jitter

引用本文复制引用

Tang Lu,Wang Zhigong,Xue Hong,He Xiaohu,Xu Yong,Sun Ling..A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits[J].半导体学报,2010,31(5):106-113,8.

基金项目

Project supported by the Specialized Research Fund for the Doctoral Program of Higher Education,China (No.20090092120012),the National Natural Science Foundation of China (No.60901012),and Natural Science Foundation of Jiangsu Province,China(No.BK2009153) （No.20090092120012）

半导体学报

OA北大核心CSCDCSTPCDEI

ISSN：1674-4926

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