首页|期刊导航|哈尔滨工业大学学报（英文版）|Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes
哈尔滨工业大学学报（英文版）2010，Vol.17Issue(5)：726-730,5.
Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes
Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes
摘要
Abstract
This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.关键词
memory/multiple bit upsets/improved hamming codes/two-dimensional error codesKey words
memory/multiple bit upsets/improved hamming codes/two-dimensional error codes分类
信息技术与安全科学引用本文复制引用
ZHU Ming,XIAO Li-yi,TIAN Huan..Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes[J].哈尔滨工业大学学报（英文版）,2010,17(5):726-730,5.基金项目
Sponsored by the Opening Project of National Key Laboratory of Science and Technology on Reliability Physics and Application Technology of Electrical Component(Grant No.ZHD200903). （Grant No.ZHD200903）
