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Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

Ji-Xue Xiao Yong-Le Xie Guang-Ju Chen

中国电子科技2009，Vol.7Issue(4)：326-330,5.
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中国电子科技2009，Vol.7Issue(4)：326-330,5.

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

Ji-Xue Xiao 1Yong-Le Xie 2Guang-Ju Chen2

作者信息

  • 1. School of Mechanical Engineering and Automation, Xihua University, Chengdu, 610039, China
  • 2. School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, China
  • 折叠

摘要

关键词

Adder/design/digital signal processors (DSP)/low power/test

Key words

Adder/design/digital signal processors (DSP)/low power/test

引用本文复制引用

Ji-Xue Xiao,Yong-Le Xie,Guang-Ju Chen..Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI[J].中国电子科技,2009,7(4):326-330,5.

基金项目

This work was supported by the National Natural Science Foundation of China under Grant No. 90407007 and University Science Foundation of China under Grant No. R0820207. （）

中国电子科技

1674-862X

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