中国电子科技2009，Vol.7Issue(4)：336-342,7.
Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
Ashutosh Kumar Singh 1Asish Bera 2Hafizur Rahaman 3Jimson Mathew 4Dhiraj K. Pradhan4
作者信息
- 1. CS Dept., School of Engineering, Curtin University of Technology, Malaysia
- 2. School of VLSI Technology, Bengal Engg.& Sc. University, Shibpur, India
- 3. Dept. of Information Technology, Bengal Engg.& Sc. University, Shibpur, India
- 4. Computer Science Dept., University of Bristol, UK
- 折叠
摘要
关键词
Bit parallel/error correction/finite field/Reed-Solomon (RS) codes/systolic/very large scale integration (VLSI) testingKey words
Bit parallel/error correction/finite field/Reed-Solomon (RS) codes/systolic/very large scale integration (VLSI) testing引用本文复制引用
Ashutosh Kumar Singh,Asish Bera,Hafizur Rahaman,Jimson Mathew,Dhiraj K. Pradhan..Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)[J].中国电子科技,2009,7(4):336-342,7.
