工矿自动化2011，Vol.37Issue(2)：52-55,4.DOI:CNKI:32-1627/TP.20110124.1504.018
基于Nios Ⅱ的伪随机序列信号发生器IP核设计
Design of IP Core of Signal Generator of Pseudo-random Sequence Based on Nios Ⅱ
摘要
Abstract
The paper put forward a design method of IP core of signal generator of pseudo-random sequence according to Avalon bus specification of Nios Ⅱ embedded system, and introduced hardware and software designs of the IP core in details. The method uses collaborative design of software and hardware of custom component to achieve IP core design of signal generator of pseudo-random sequence with adjusted code length and order. Its feasibility and correctness were proved in design of controlled vibrating signal generator.关键词
伪随机码/信号发生器/Nios Ⅱ/SOPC Builder/Avalon总线/IP核Key words
pseudo-random sequence/ signal generator/ Nios Ⅱ/ SOPC Builder/ Avalon bus/ IP core分类
矿业与冶金引用本文复制引用
郑恭明,沈媛媛..基于Nios Ⅱ的伪随机序列信号发生器IP核设计[J].工矿自动化,2011,37(2):52-55,4.基金项目
中国石油科技创新基金项目(2008D-5006-03-07) （2008D-5006-03-07）
