电力系统及其自动化学报2011，Vol.23Issue(1)：103-107,5.
用于SVC数控系统的数字锁相环的设计与实现
Design and Realization of Digital Phase Locked Loop for Control System of SVC
张志文 1郭斌 1罗隆福 1曾志兵 1王伟1
作者信息
- 1. 湖南大学电气与信息工程学院,长沙410082
- 折叠
摘要
Abstract
In order to reduce the thyristor triggering error in the static var compensator (SVC), all digital phase-locked loop(ADPLL) is designed based on field programmable gate array(FPGA). Principle of each module is analyzed ,and the parameter design and the circuit simulation are completed. Finally, it is tested on experimental platform. The result shows that the ADPLL can stably track power network signal. It provides fast, stable and accurate synchronized signal for the SVC numerical control system.关键词
全数字锁相环/静止无功补偿装置/触发误差/现场可编程门阵列/同步信号Key words
all digital phase locked loop(ADPLL) / static var compensator (SVC) / triggering error/ field programmable gate array (FPGA)/ synchronized signal分类
信息技术与安全科学引用本文复制引用
张志文,郭斌,罗隆福,曾志兵,王伟..用于SVC数控系统的数字锁相环的设计与实现[J].电力系统及其自动化学报,2011,23(1):103-107,5.
