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A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

Jiao Yishu Zhou Yumei Jiang Jianhua Wu Bin

半导体学报2010，Vol.31Issue(9)：74-78,5.

半导体学报2010，Vol.31Issue(9)：74-78,5.DOI:10.1088/1674-4926/31/9/095002

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

Jiao Yishu ¹Zhou Yumei ¹Jiang Jianhua ¹Wu Bin¹

作者信息

1. Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China
折叠

摘要

关键词

phase-locked loop/phase noise/regulator/ring oscillator/CMOS

Key words

phase-locked loop/phase noise/regulator/ring oscillator/CMOS

引用本文复制引用

Jiao Yishu,Zhou Yumei,Jiang Jianhua,Wu Bin..A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs[J].半导体学报,2010,31(9):74-78,5.

基金项目

Project supported by the National Key Project of New Generation Broadband Wireless Mobile Communication Network,China (No.2009ZXO3007-002-03). （No.2009ZXO3007-002-03）

半导体学报

OA北大核心CSCDCSTPCDEI

ISSN：1674-4926

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