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A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

Chen Hu Lu Bo Shao Ke Xia Lingli Huang Yumei Hong Zhiliang

半导体学报2010，Vol.31Issue(1)：46-50,5.

半导体学报2010，Vol.31Issue(1)：46-50,5.DOI:10.1088/1674-4926/31/1/015001

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

Chen Hu ¹Lu Bo ¹Shao Ke ¹Xia Lingli ¹Huang Yumei ¹Hong Zhiliang¹

作者信息

1. State Key Laboratory of ASIC & System,Fudan University,Shanghai 201203,China
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摘要

关键词

PLL/in-band noise/dynamic mismatch/RMS jitter

Key words

PLL/in-band noise/dynamic mismatch/RMS jitter

引用本文复制引用

Chen Hu,Lu Bo,Shao Ke,Xia Lingli,Huang Yumei,Hong Zhiliang..A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology[J].半导体学报,2010,31(1):46-50,5.

基金项目

Project supported by the National High Technology Research and Development Program of China (No. SQ2008AA01Z4473469). （No. SQ2008AA01Z4473469）

半导体学报

OA北大核心CSCDCSTPCDEI

ISSN：1674-4926

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