高技术通讯2011，Vol.21Issue(4)：434-437,4.DOI:10.3772/j.issn.1002-0470.2011.04.018
应用于GPS频率综合器的可编程分频器的设计
Design of a programmable frequency divider in GPS frequency synthesizers
摘要
Abstract
A digital CMOS programable frequency divider .used in 1.2GHz frequency syntbesizers for global position system (GPS) transceivers was designed. The frequency divider achieves a dividing ratio in the range of 600 to 700, and achieves a better duty cycle of the output wave form by using a proved even frequency dividing algorithm. The design was carried out according to the standard ASIC design flows, such as Verilog coding, lngic synthesizing, layout planing, detailed routing, and post-layout simulation analyzing. The proposed structure, with its core chip area being ll5μm ×115μm was simulated and implemented using a standard SMIC 0.18μm CMOS logic process model and the experimental result shows that it can match the control port and work with a correct dividing ratio by the setting logic, so can accordingly achieve the expected result.关键词
全球定位系统(GPS)/频率综合器/可编程分频器/均匀分频算法/CMOSKey words
global position system (GPS)/ frequency synthesizer/ programmable frequency divider/ even frequency dividing algorithm/ CMOS引用本文复制引用
陈莹梅,景永康,章丽..应用于GPS频率综合器的可编程分频器的设计[J].高技术通讯,2011,21(4):434-437,4.基金项目
863计划(2006AA01Z239)和国家自然科学基金(60976029)资助项目. （2006AA01Z239）
