西安电子科技大学学报（自然科学版）2011，Vol.38Issue(3)：76-82,7.DOI:10.3969/j.issn.1001-2400.2011.03.013
一种用于人脸检测SoC中的加速协处理器设计
Co-processor implementation for fast face detection in a system-on-chip
摘要
Abstract
An improved co-processor architecture suitable for hardware parallel implementation is proposed to perform the feature classification based on the Adaboost algorithm. The co-processor consists of image quick access module, module for calculating the Haar features, DMA data transfer module, and interface to the coprocessor module. Modules use the pipeline and FIFO buffer to process data to accelerate the iterative process of face detection. The co-processor only increases a small area in face detection SoC, but significantly improves the speed of face detection. In addition, we implement the proposed SoC on a CYCLONE-Ⅱ EP2C70 FPGA to show that object detection can be achieved at 10 frames per second at the system operating frequency of 70 MHz on color QVGA camera video.关键词
人脸检测/Adaboost算法/多层分类器/协处理器Key words
face detection/ Adaboost algorithm/ features classifiers/ co-processor分类
信息技术与安全科学引用本文复制引用
焦继业,穆荣,郝跃..一种用于人脸检测SoC中的加速协处理器设计[J].西安电子科技大学学报（自然科学版）,2011,38(3):76-82,7.基金项目
陕西省自然科学基金资助项目(2009JM8004) （2009JM8004）
