计算机工程2011，Vol.37Issue(10)：219-221,3.DOI:10.3969/j.issn.1000-3428.2011.10.076
一种改进的反码加法器设计
Design of Improved One's Complement Adder
唐敏 1许团辉 2王玉艳2
作者信息
- 1. 上海交通大学微纳科学技术研究院,上海,200030
- 2. 华东计算技术研究所,上海,200233
- 折叠
摘要
Abstract
Conventional adder adding the required number of.signed operands into the form of complement operations, and return a result in signed magnitude number. This paper proposes a new structure one's complement Signed Adder(SA) based on the flagged prefix adder, which could combine the increment unit with the adder, to reduce the delay of the signed adder. A 64-bits enhanced SA has been implemented in SMIC 180nm CMOS technology. Compared with previous work, the area, power, and delay of our design are decreased by 39.1％, 39.9％, and 5.1％, respectively.Results show that this structure is superior to two's complement adder.关键词
加法器/有符号加法器/反码/补码Key words
adder/ Signed Adder(SA)/ one's complement/ two's complement分类
信息技术与安全科学引用本文复制引用
唐敏,许团辉,王玉艳..一种改进的反码加法器设计[J].计算机工程,2011,37(10):219-221,3.
