计算机与数字工程2011，Vol.39Issue(4)：44-46,3.
基于FPGA的18b20的CRC校验码的并行算法及实现
Inplementation of the Parallel Algorithm of CRC Check Cooles in 18b20 Based on FPGA
摘要
Abstract
Based on analysis of the structure of serial CRC generation algorithm, an efficient parallel 8-bit CRC-8 generation algorithm is studied in the paper. And CRC-8 checksum module of 18B20 56bit address is achieved with FPGA and Verilog language.关键词
并行算法/18b20/CRC-8/Verilog/FPGAKey words
parallel algorithm/ 18b20/ CRC-8/ Verilog/ FPGA分类
信息技术与安全科学引用本文复制引用
张锦鹏,程明,王俊山..基于FPGA的18b20的CRC校验码的并行算法及实现[J].计算机与数字工程,2011,39(4):44-46,3.
